Researchers unlock faster chip math by rethinking how FPGAs add numbers
Engineers have redesigned how field-programmable gate arrays perform basic arithmetic, cutting processing delays in half for large calculations without using extra hardware. The breakthrough matters for companies deploying FPGAs in data centers, networking, and AI accelerators—where speed directly affects competitive advantage and power costs.
Originaltitel: Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs
<p>Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented by letting some cells calculate the carry chain in two bits per cell, while some others calculate the summary output bits. In total the proposed design uses no more hardware than the normal adder. The result shows that the proposed adder is faster than a normal adder for word length larger than 64 bits in Virtex-6 FPGAs.</p>