New chip design cuts latency for wireless networks by 25 microseconds
Researchers have demonstrated hardware that can intelligently route data across multiple wireless networks simultaneously while maintaining near-instant response times. The breakthrough matters for carriers and enterprises seeking to improve network reliability and speed without costly infrastructure overhauls.
Originaltitel: Accelerating Transport Layer Multipath Packet Scheduling for 5G-ATSSS
<p>Utilizing multiple access networks such as 5G, 4G, and Wi-Fi simultaneously can lead to increased robustness, resiliency, and capacity for mobile users. However, transparently implementing packet distribution over multiple paths within the core of the network faces multiple challenges including scalability to a large number of customers, low latency, and high-capacity packet processing requirements. In this paper, we offload congestion-aware multipath packet scheduling to a smartNIC. However, such hardware acceleration faces multiple challenges due to programming language and platform limitations. We implement different multipath schedulers in P4 with different complexity in order to cope with dynamically changing path capacities. Using testbed measurements, we show that our CMon scheduler, which monitors path congestion in the data plane and dynamically adjusts scheduling weights for the different paths based on path state information, can process more than 3.5 Mpps packets 25 μs latency.</p>